Integrated circuit arrangement with feature control

ABSTRACT

An integrated circuit arrangement is reconfigurable in the field to operate in one of a plurality of modes, including a test mode, in response to mode-selecting codes presented via a temporary register in the circuit. In one example embodiment, an arrangement of integrated circuits includes a reconfigurable integrated circuit configured and arranged to operate in one of a plurality of modes. The reconfigurable integrated circuit includes a register adapted to store data for temporary use, with each operating mode of the reconfigurable circuit being selectable in response to mode-selecting data code. An interface circuit is electrically connected to the reconfigurable integrated circuit and is adapted to present the mode-selecting data code to the reconfigurable integrated circuit. A selection circuit is adapted to enable the interface circuit to pass mode-selecting data to the reconfigurable integrated circuit. The selection circuit is also adapted to detect when a series of data writes to the register corresponds to the mode-selecting data code and, in response, to reconfigure the integrated circuit to operate in one of the plurality of modes.

FIELD OF THE INVENTION

The present device relates generally to integrated circuit devices and,in particular, to an integrated circuit arrangement that isreconfigurable to operate in alternate modes, for use with various CPUsand peripherals.

BACKGROUND OF THE INVENTION

Programmable integrated circuit devices have long played a key role inthe design of digital hardware. Most are general-purpose chips that canbe configured for a wide variety of applications. Some of theseintegrated circuit devices include, for example, Programmable Read-onlyMemory (PROM), Erasable Read-only Memory (EPROM), Programmable LogicDevices (PLDs), Field Programmable Gate Arrays (FPGAs) and MaskProgrammable Gate Arrays (MPGAs).

FPGAs, in particular, are not only programmable but are actuallycomputing integrated circuit devices that can implement virtually anydigital circuit in hardware. FPGAs provide an end user with ability todirectly configure the logic structure on the chip without the need foran integrated circuit fabrication facility. FPGAs can also bereprogrammed simply by loading them with a different “hardware program.”The reprogramming feature of the FPGA facilitates implementing manyprocessing algorithms with performance that simulates dedicated hardwarewhile retaining the flexibility of dynamically reconfiguring theimplementation when necessary. However, re-programming is time consumingand, depending on the application, using FPGAs can be expensive.

Another integrated circuit device used in computing is a universalasynchronous receiver/transmitter (UART) device. A UART is a datacommunications device that performs parallel-to-serial conversion ofdigital data. A UART communicates between parallel and serial forms byconverting received data between parallel I/O devices, such as a localCPU, and serial I/O devices, such as POTS modems or other transmissionlines. Most traditional UART devices can be programmed to operate at aselected baud rate, and the newer generation UARTs handle datacommunication more efficiently, to a great extent due to larger FIFOdepths and improved flow control (fewer retries required and fewer waitsfor the internal FIFO to fill or empty). However, for many applications,reprogramming the functionality of a UART device in the field can beproblematic because most of the hardwire connections of the UART arepermanently configured at the factory before the device is shipped.

It would be highly desirable to have an arrangement of integratedcircuits that is reconfigurable in the field to operate in alternatemodes without adding additional hardware or expense.

SUMMARY OF THE INVENTION

Various aspects of the present invention are directed to facilitatingefforts to reconfigure integrated circuit device functionality in thefield. The present invention is exemplified in a number ofimplementations and applications, some of which are summarized below.

According to an example embodiment of the present invention, anarrangement of integrated circuits includes a reconfigurable integratedcircuit configured and arranged to operate in one of a plurality ofmodes. The reconfigurable integrated circuit includes a register adaptedto store data for temporary use, with each operating mode of thereconfigurable circuit being selectable in response to mode-selectingdata code. An interface circuit is electrically connected to thereconfigurable integrated circuit and is adapted to present themode-selecting data code to the reconfigurable integrated circuit. Aselection circuit is adapted to enable the interface circuit to passmode-selecting data to the reconfigurable integrated circuit. Theselection circuit is also adapted to detect when a series of data writesto the register corresponds to the mode-selecting data code and, inresponse, to reconfigure the integrated circuit to operate in one of theplurality of modes.

A more particular implementation of the present invention provides asecurity feature that prohibits unauthorized attempts to reconfigure theintegrated circuit when the selection circuit and the register do notdetect an operative mode-selecting data code.

The above summary is not intended to describe each illustratedembodiment or every implementation of the present invention. The figuresand detailed description that follow more particularly exemplify theseembodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be more completely understood in consideration of thefollowing detailed description of various embodiments of the inventionin connection with the accompanying drawing, in which:

FIG. 1 is a block diagram of an arrangement of integrated circuitdevices that includes at least one reconfigurable integrated circuitresponsive to mode-selecting codes, according to an example embodimentof the present invention; and

FIG. 2 is a diagram of a finite state machine exhibiting the writing ofmode-selecting data into a temporary register, according to anotherexample embodiment of the present invention.

While the invention is amenable to various modifications and alternativeforms, specifics thereof have been shown by way of example in thedrawing and will be described in detail. It should be understood,however, that the intention is not to limit the invention to theparticular embodiments described. On the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

The present invention is generally directed to a reconfigurableintegrated circuit that operates in one of a plurality of modes,including a test mode, in response to mode-selecting data codespresented in a temporary register in the circuit. The present inventionis particularly advantageous for, but is not necessarily limited to,UART and FPGA devices; other reconfigurable integrated circuits such asPLDs and MPGAs also realize benefit. While the present invention is notlimited to such circuits, an appreciation of various aspects of theinvention is best gained through a discussion of various examples usingthis application.

According to an example embodiment of the present invention, anarrangement of integrated circuits includes a feature-enabled circuit aspart of a programmable and semi-programmable chip that is configured andarranged to operate in one of a plurality of modes. In particular, thefeature-enabled circuit includes a scratchpad register adapted to storedata for temporary use, with each feature (or operating mode) of thefeature-enabled circuit being selectable in response to mode-selectingdata code. The feature-enabled circuit is adapted to present themode-selecting data code to the feature-enabled circuit. A selectioncircuit detects when a series of data writes to the scratchpad registercorresponds to an instruction to enable a selected feature of thefeature-enabled circuit. In an example application, the consecutive datawrites to the scratchpad register reconfigure the feature-enabledcircuit to increase the address map space.

In another embodiment, the feature-enabled circuit is a UART circuitthat uses its scratchpad register to receive an instruction to enable aflow control circuit. The flow control circuit indicates the flowcondition for data passing through the UART's internal FIFO duringcommunication. In various implementations the flow conditions of theUART include one or more of the following: whether the FIFO registers ofthe serial communication circuit are full or empty; whether thetransmit/receive registers have reached an upper or lower thresholdlevel; or whether an error has occurred, due to, for example, the FIFOoverflowing or invalid data being drawn from the FIFO. In a relatedembodiment, the scratchpad receives an instruction to operate the UARTwith an extendible FIFO.

In another particular embodiment, the integrated circuit arrangementfurther includes a CPU that is communicatively coupled to thefeature-enabled circuit via a parallel data bus. The nonvolatile memory,such as a flash memory or an EPROM, is adapted to store a key code usedby the selection circuit to detect the series of data writes to theregister.

Referring now to the figures, FIG. 1 is a block diagram of anarrangement 100 of integrated circuit devices that includesreconfigurable integrated circuits responsive to mode-selecting datacodes, according to an example embodiment of the present invention. Inthis example embodiment, arrangement 100 reconfigures an integratedcircuit to operate in a test mode or to operate with one or more of aseries of features that are enabled in the field.

In this particular example embodiment, arrangement 100 includes a CPU110 communicatively coupled to a UART circuit 130 and to a fieldprogrammable gate array (FPGA) 140 via a parallel data bus 120. CPU 110is configured to include a memory management unit (not shown) thatprovides the address, data and control signals for communicating withcircuits 130 and 140, respectively. In this example, UART circuit 130and FPGA 140 are each reconfigurable to operate in different modesdepending on a mode-selecting data code received by either circuit viaparallel data bus 120.

In one example embodiment, UART circuit 130 operates in either a testmode or in a different operating mode in response to a mode-selectingcode received through a temporary storage register 132. In thisparticular example, register 132 is a scratchpad register thattemporarily stores and retrieves bytes of data. A selection circuit 134transmits the mode-selecting data from CPU 110 to scratchpad register132. The mode-selecting data passes through selection circuit 134 as aseries of data writes to register 132 that correspond to amode-selecting code, or an instruction, which enables or disables afeature of UART circuit 130. CPU 110 sends a key code (or mode-selectingcode) to reconfigure UART circuit 130 by sending consecutive writes toregister 132. Selection circuit 134 monitors the consecutive data writesthrough register 132 to determine which features are enabled/disabled orif UART circuit 130 is to transition to a test mode. In one exampleapplication, consecutive writes of “DE-B0-01” enables the extendibleflow control circuit of the UART.

In another embodiment, consecutive writes to register 132 reconfigureUART circuit 130 to increase the address map space for the FIFO by“folding” the address map to expose more address map space. Each“folding” of the address map doubles the address map space.

In another example embodiment, consecutive writes to register 132correspond to a different code that transitions the UART into either atest mode or a diagnostic mode.

In another example embodiment, FPGA circuit 140 is configured to includea temporary register 142 and a selection circuit 144 that reconfigurescircuit 140 to operate in different modes. Similar to the previouslydiscussed example of UART circuit 130, a selection circuit 144 transmitsthe mode-selecting data from CPU 110 to a common register 142.Corresponding to a mode-selecting code, the mode-selecting data passesthrough selection circuit 144 as a series of data writes to register142. In this example, the mode-selecting code is an instruction thatenables or leaves disabled certain logic circuits within FPGA circuit140. CPU 110 sends a key code to reconfigure FPGA circuit 140 by sendingconsecutive writes to register 142. Selection circuit 144 monitors theconsecutive data writes through register 142 to determine which logiccircuits are enabled or left disabled.

Referring now to FIG. 2, a diagram of a finite state machine (FSM) 200illustrates the process of writing mode-selecting data into a temporaryregister, according to another example embodiment of the presentinvention. For purposes of the following examples, a two-part code isused as an example mode-selecting data code. However, the mode-selectingcode is not necessarily limited to a two-part code and can include codesof varying length that reference an instruction for reconfiguring thevarious circuits previously described.

In this example, at state 202 of FSM 200, selection circuit 134 monitorsdata writes to detect the first part of a two-part mode-selecting code(e.g, M(1), M(2)) as the data is being written to a register 132. In theinitial state, selection circuit 134 and register 132 verify that thedata written (representing the first part of the mode-selecting code) iscorrect (i.e, DATA=M(1)). Once the first part of the code is verified asbeing correct, FSM 200 transitions to state 204 where register 132 andcircuit 134 monitor and verify that the data written (representing thesecond part of the mode-selecting code) is correct (i.e, DATA=M(2)).Monitoring at state 204 continues until the second part of the two-partcode is verified as being correct. In this example, once the two-partcode is verified as being correct FSM 200 transitions to state 206. Atstate 206, the first feature of UART circuit 130 is enabled becauseregister 132 and circuit 134 received the correct mode-selecting codefor enabling the first feature of the UART circuit. After enabling thefirst feature, FSM 200 transitions from state 206 to state 212, whereregister 132 and circuit 134 reset the two-part code (M1, M2). Afterresetting the two-part code, FSM 200 transitions from state 212 to state202 where monitoring for a new mode-selecting code commences once again.

In a related embodiment, at state 208, a third feature of UART circuit130 is enabled upon register 132 and circuit 134 receiving the correctmode-selecting code. Once the feature is enabled, FSM 200 transitions tostate 212 and then to state 202, where register 132 and circuit 134reset the two-part code and monitoring for a new mode-selecting codecommences, respectively.

In another embodiment, register 132 and circuit 134 monitor and verifythe mode-selecting code for reconfiguring the feature-enabled circuit tooperate in a test mode (e.g., DATA=M(T)). Upon verifying the test modecode at states 202 and 204 (DATA=M(T)), the feature-enabled circuit isreconfigured into the test mode at state 210. After reconfiguring intothe test mode, FSM 200 transitions from state 210 to state 212 to resetthe two-part code and then to state 202 to commence monitoring datawrites to register 132. In this example, the feature-enabled circuitcontinues in the test mode until selection circuit 134 detects anothermode-selecting code that reconfigures the feature-enabled circuit tooperate in a new mode.

In most of the above examples, the feature-enabled circuit has asecurity feature to prevent unauthorized reconfiguration. In aparticular embodiment, the feature-enabled circuit cannot bereconfigured where the selection circuit and the register do not detecta recognizable mode-selecting data code (i.e., DATA does not equal M(2);M(T); or M(3)) at either state 202 or state 204. In this exampleembodiment, where neither part of the code is verified as being correctat both state 202 and state 204, FSM 200 transitions from state 204 tostate 212 such that M(1) and M(2) are each reset to their initialstates. At state 202, monitoring at selection circuit 134 restarts formode-selecting data codes being written to register 132.

Several of the above embodiments can be implemented by modifyingcommercially available UART devices to include the above-describedoperation. For further details on such commercially-available componentsand their modes of operation, reference may be made to ProductSpecifications, No. 853-1585-23061 (Jan. 31, 2000) and No.853-1078-19971 (Sep. 4, 1998), for UART part numbers SCC2691AC1A28 andSC26C92A1A; each being commercially available from Philips Semiconductorand incorporated herein by reference.

It will also be appreciated that the above-described aspects of thepresent invention can be combined structurally and/or functionally withone or more of the aspects described in concurrently—filed U.S.application Ser. No. 09/870,917 (VLSI.315PA), Ser. No. 09/870,918(VLSI.316PA), and Ser. No. 09/871,027 (VLSI.318PA).

While the present invention has been described with reference to severalparticular example embodiments, those skilled in the art will recognizethat many changes may be made thereto without departing from the spiritand scope of the present invention, which is set forth in the followingclaims.

What is claimed is:
 1. An arrangement of integrated circuits,comprising: a reconfigurable integrated circuit including a universalasynchronous receiver/transmitter that is configured and arranged tooperate in one of a plurality of data communication modes and includinga register adapted to store data for temporary use, each datacommunication mode being selectable in response to mode-selecting datacode; an interface circuit electrically connected to the reconfigurableintegrated circuit and adapted to present the mode-selecting data codeto the reconfigurable integrated circuit; and a selection circuitadapted to enable the mode-selecting data to be passed from theinterface circuit to the reconfigurable integrated circuit, theselection circuit adapted to detect when a series of data writes to theregister corresponds to the mode-selecting data code and, in response,reconfiguring the integrated circuit to operate in one of the pluralityof data communication modes.
 2. The arrangement of claim 1, wherein theregister is commonly used in multiple ones of the plurality of modes. 3.The arrangement of claim 2, wherein the reconfigurable integratedcircuit is a universal asynchronous receiver/transmitter, and theregister is a scratchpad register.
 4. The arrangement of claim 1,wherein the reconfigurable integrated circuit includes afield-programmable gate array.
 5. The arrangement of claim 1, whereinthe selection circuit is further adapted to detect when a series of datawrites to the register corresponds to a test mode for the integratedcircuit.
 6. The arrangement of claim 1, wherein the selection circuit isfurther adapted to detect when a series of data writes to the registercorresponds to an instruction to enable a mode for the integratedcircuit.
 7. The arrangement of claim 1, wherein the selection circuit isfurther adapted to detect when a series of data writes to the registercorresponds to an instruction to disable a mode for the integratedcircuit.
 8. An arrangement of integrated circuits comprising: areconfigurable integrated circuit including a universal asynchronousreceiver/transmitter; configured and arranged to operate in one of aplurality of modes and including a register where the register is ascratchpad register adapted to store data for temporary use, each modebeing selectable in response to mode-selecting data code, and whereinthe universal asynchronous receiver/transmitter includes an extendibleFIFO having one of a plurality of sizes selectable by the mode-selectingdata; an interface circuit electrically connected to the reconfigurableintegrated circuit and adapted to present the mode-selecting data codeto the reconfigurable integrated circuit; and a selection circuitadapted to enable the mode-selecting data to be passed from theinterface circuit to the reconfigurable integrated circuit, theselection circuit adapted to detect when a series of data writes to theregister corresponds to the mode-selecting data code and, in response,reconfiguring the integrate circuit to operate in one of the pluralityof modes.
 9. The arrangement of claim 1, wherein the reconfigurableintegrated circuit is a universal asynchronous receiver/transmitter, theregister is a scratchpad register and the selection circuit is furtheradapted to detect when a series of data writes to the registercorresponds to an instruction to disable a mode for the integratedcircuit.
 10. An arrangement of integrate circuits, comprising: areconfigurable integrated circuit including a universal asynchronousreceiver/transmitter; configured and arranged to operate in one of aplurality of modes and including a register where the register is ascratchpad register adapted to store data for temporary use, each modebeing selectable in response to mode-selecting data code and wherein(the universal asynchronous receiver/transmitter includes a flow-controlcircuit adapted to be enabled by the mode-selecting data; an interfacecircuit electrically connected to the reconfigurable integrated circuitand adapted to present the mode-selecting data code to thereconfigurable integrated and a selection circuit adapted to enable themode-selecting data to be passed from the interface circuit to thereconfigurable integrated circuit, the selection circuit adapted todetect when a series of data writes to the registers corresponds to themode-selecting data code and, in response, reconfiguring the integratedcircuit to operate in one of the plurality of modes.
 11. An arrangementof integrated circuits comprising: a reconfigurable integrated circuitincluding a universal asynchronous receiver/transmitter; configured andarranged to operate in one of a plurality of modes and including aregister where the register is a scratchpad register adapted to stowdata for temporary use, each mode being selectable in response tomode-selecting data code, and wherein the universal asynchronousreceiver/transmitter includes an extendible Hit having one of aplurality of sizes selectable by the mode-selecting data, and whereinthe universal asynchronous receiver/transmitter includes a flow controlcircuit adapted to be enabled by the mode-selecting data and to indicateat least one flow-status condition of the FIFO; an interface circuitelectrically connected to the reconfigurable integrated circuit andadapted to present the mode-selecting data code to the reconfigurableintegrated circuit; and a selection circuit adapted to enable themode-selecting data to be passed from the interface circuit to thereconfigurable integrated circuit the selection circuit adapted todetect when a series of data writes to the register corresponds to themode-selecting data code and, in response, reconfiguring integratedcircuit to operate in one of the plurality of modes.
 12. The arrangementof claim 11, further including a parallel data bus, and a CPU that iscommunicatively coupled to the universal asynchronousreceiver/transmitter via the parallel data bus.
 13. The arrangement ofclaim 12, wherein the interface circuit is adapted to couple theuniversal asynchronous receiver/transmitter to the parallel data bus forcommunication with the CPU, and wherein the universal asynchronousreceiver/transmitter further includes a nonvolatile memory adapted tostore a key code used by the selection circuit to detect the series ofdata writes to the register.
 14. An arrangement of integrated circuits,comprising: a reconfigurable integrated circuit including a universalasynchronous receiver/transmitter that is configured and arranged tooperate in one of a plurality of data communication modes and includingstorage means for storing data temporarily, each data communication modebeing selectable in response to mode-sub tag data code; interface means,electrically connected to the reconfigurable integrated circuit, forpresenting the mode-selecting data rode to the reconfigurable integratedcircuit; and means for enabling the mode-selecting data to bc passedfrom the interface circuit to the reconfigurable integrated circuit, andfor detecting when a series of data writes to the register correspondsto the mode-selecting data code and, in response, reconfiguring theintegrated circuit to operate in one of the plurality of datacommunication modes.